The modern high speed LSI circuit is more and more sensitive to clock signal. Apart from clock jitter, clock duty cycle has a crucial effect on the performance of high speed LSI circuits. So, clock signal with 50% duty cycle is very important in designing high speed LSI circuits, For instance, in high speed analog-to-digital converter and dual data rate SDRAM, as rising-edge and falling-edge of clock was used, clock signal with 50% duty cycle is critical to the system. For high speed dynamic circuit, duty cycle, which determines pre-charging and evaluation time, has huge impact on its performance. Usually, the duty cycle of PLL VCO's clock signal would deviate from 50% due to device mismatch. To obtain 50% duty cycle clock signal, the conventional method is to perform a +2 frequency division of output signal of PLL VCO by frequency divider, which, however, would require that the VCO have oscillating frequency to be doubled clock frequency, making the design of PLL more difficult.
At present, duty cycle correction circuit is usually adopted to fulfill this function. The PLL VCO usually output double ended signals, so double to single ended conversion circuit is employed for application of single ended clock.